1. Field of the Invention
This invention relates to a trimming circuit for a physical quantity sensor.
2. Description of the Prior Art
To reduce the number of input terminals of a trimming circuit for a physical quantity sensor, a signal separation circuit for separating control signals is used. FIG. 8 shows a prior art trimming circuit 101 for a physical quantity sensor. The trimming circuit 101 includes a logic circuit 102 for generating control signals on the basis of input signals, and a trimming voltage control circuit 103 for storing data on the basis of the control signals from the logic circuit 102 and generating trimming voltages for trimming the sensor outputs on the basis of the stored data. The trimming voltage control circuit 103 includes a plurality of memory blocks 103a, each having an address decoder, an input/output controller, a latch (volatile memory), and a PROM (non-volatile memory), an error correction circuit 103b for correcting the data stored in the memory, and a D/A converter 103c for converting the error-corrected output into an analog signal.
The trimming circuit 101 has three trimming signal input terminals 104 to 106. That is, the Clock/Reset terminal 104 inputs a Clock/Reset signal including a Clock signal and a Reset signal, the DATA terminal 105 inputs a DATA signal with logic Hi (=VDD) and Low (=GND) levels in phase with the clock signal, and the VPP terminal 106 inputs a high voltage VPP supplied to memories such as EPROM in the trimming voltage control circuit 103.
The trimming circuit 101 includes a signal separation circuit 107 for separating the Clock/Reset signal into the Clock signal and the Reset signal which are supplied to the logic circuit together with the DATA signal. The logic circuit 102 supplies address data, a mode control signal, and data corresponding to the DATA signal to the trimming voltage control circuit 103. The trimming voltage control circuit 103 generates trimming voltages for trimming the sensor output.
The high voltage VPP from the VPP terminal is supplied when data is written in the memory in the trimming voltage control circuit 103. On the other hand, while the writing operation is not effected, the supply voltage VDD is supplied to the trimming voltage control circuit 103 from a regulated voltage supply (not shown).
FIG. 9 shows a time chart of an example of the trimming of the physical sensor. Three voltage levels represent the Clock/Reset signal. The GND level represents resetting the logic circuit 102, a one-half of VDD represents the release of the resetting the logic circuit 102 and a logic Low level of the Clock signal, and the VDD level represents the release of the resetting the logic circuit 102 and a logic Hi level of the Clock signal. The DATA signal represents data with either of the Hi and Low logic levels. In response to the DATA signal, the logic circuit 102 successively makes temporarily storing data in the latch, reading data in the latch, writing the data in the PROM, and reading data in the PROM in the trimming voltage control circuit 103 on the basis of the DATA signal. Although the high voltage VPP signal is fixedly shown in FIG. 6, in fact, the high voltage VPP is supplied to the trimming voltage control circuit 103 only when data is written in the PROM.
This prior art trimming circuit 101 has three inputs in addition to the Vcc terminal, the GND terminal, and the Vout terminal 5. Thus, the reduction of the number of input terminals is further required.
Moreover, to correct an error in the data stored in the memory in the trimming circuit, a majority decision circuit is used.
FIG. 10A shows a prior art majority decision circuit 101 provided to the memory circuit. FIG. 10B shows a truth table of the majority decision circuit 201. On reading the memory, data A1, A2, and A3 of which values are to be the same are inputted to the majority decision circuit 201. When more than one pieces of the data indicate xe2x80x9c1xe2x80x9d, the majority decision circuit 201 outputs xe2x80x9c1xe2x80x9d. When more than one pieces of the data indicate xe2x80x9c0xe2x80x9d, the majority decision circuit 201 outputs xe2x80x9c0xe2x80x9d. Then, although one piece of the data is erroneously read or written, the data is corrected.
Each bit of output of the memories is subjected to the majority decision to provide a high reliability as shown in a prior art error correction circuit in FIG. 8.
However, the bit efficiency (the number of input bits per one output bit) in this circuit is low because a greater number of input bits are required. Thus, an error correction circuit having a higher bit efficiency is required in the trimming circuit.
The aim of the present invention is to provide a superior trimming circuit for a physical quantity sensor.
According to the present invention, a first aspect of the present invention provides a trimming circuit for a physical quantity sensor comprising:
an analog circuit for effecting at least one of an adjustment operation of a supply voltage to said physical quantity sensor and a trimming operation for an output voltage of said physical quantity sensor in accordance with a trimming value;
a trimming value control circuit having a memory circuit for storing data and generating said trimming value in accordance with said data from said memory;
a trimming signal input terminal for inputting a control signal including a clock signal, a reset signal, and said data as components;
a signal separation circuit for separating said clock signal, said reset signal, and said data from said control signal; and
a logic circuit in response to said clock signal and said reset signal for supplying said data from said signal separation circuit to said trimming value control circuit and for receiving said data from said trimming value control circuit.
According to the present invention, a second aspect of the present invention provides a trimming circuit based on the first aspect, wherein said control signal further includes a writing voltage for said memory circuit as a component, and said signal separation circuit further separates said writing voltage from said control signal.
According to the present invention, a third aspect of the present invention provides a trimming circuit based on the first aspect, further comprising a power supply terminal for inputting a driving voltage for said physical quantity sensor, a ground terminal, and an output terminal for outputting a voltage signal corresponding to an output of said physical quantity sensor, and thus said trimming circuit having only four terminals.
According to the present invention, a fourth aspect of the present invention provides a trimming circuit based on the third aspect, further comprising a voltage generation means for generating a predetermined voltage level signal of which level is determined on the basis of said data from said logic circuit, and a switch response to said data for outputting either of said voltage signal or said predetermined voltage level signal, wherein said predetermined voltage level signal is distinguishable from said voltage signal.
According to the present invention, a fifth aspect of the present invention provides a trimming circuit based on the fourth aspect, wherein said power supply terminal, said ground terminal, and said output terminal are connected to said analog circuit, and said logic circuit includes a decoding circuit for decoding said data to generate mode setting data, address data, and control data, said logic circuit supplies said control data to said trimming value control circuit as said data in accordance with said mode setting data and address data, and wherein when said mode setting data indicates a predetermined voltage level signal outputting mode, said logic circuit receives said data from said memory circuit and supplies said received data to said analog circuit and controls said switch to output said predetermined voltage level signal at said output terminal on the basis of said data from said logic circuit.
According to the present invention, a sixth aspect of the present invention provides a trimming circuit based on the first aspect, wherein said control signal is represented with first to fourth voltages levels, said fourth level is higher than said third voltage level which is higher than said second voltage level which is higher than said first voltage level, and wherein said logic circuit effects a reset operation thereof in response to said first voltage level, effects a reset releasing operation thereof in response to said second voltage level, receives said second voltage level as a logic Low level of said clock signal and a logic Low level of said data, and effects said reset releasing operation of said logic circuit in response to said third voltage level, receives said third voltage level as a logic Hi level of said clock signal, and a logic Low level of said data, and effects said reset releasing operation of said logic circuit in response to said fourth voltage level, receives said fourth voltage level as said logic Hi level of said clock signal, and a logic Hi level of said data.
According to the present invention, a seventh aspect of the present invention provides a trimming circuit based on the second aspect, wherein said writing voltage is higher than a supply voltage for said signal separation circuit, said trimming voltage control circuit, and said logic circuit, and wherein said signal separation circuit includes first and second diodes for supplying either said supply voltage or said writing voltage, an anode of said first diode being connected to said trimming signal input terminal, a cathode of said first diode being connected to a voltage input of said trimming voltage control circuit, an anode of said second diode being supplied with said supply voltage, a cathode of said second diodes being connected to said voltage input of said trimming voltage control circuit.
According to the present invention, an eighth aspect of the present invention provides a trimming circuit based on the first aspect, wherein said memory circuit includes a plurality of memory blocks for storing said data including first and second data, each of said memory blocks including a memory; and said trimming value control circuit comprises:
a first error correction circuit for error-correcting said first data from said memory circuit through a first error correcting method;
a second error correction circuit for error-correcting said second data from said memory circuit through a second error correcting method, said first error correcting method being different from said second error correcting method; and
a weighting circuit for weighting an output of said first error correction circuit with a first coefficient to output a first trimming value and an output of said second error correction circuit with a second coefficient to output a second trimming value, said first coefficient being higher than said second coefficient, said logic circuit supplying said first and second trimming values as said trimming value to said analog circuit.
According to the present invention, a ninth aspect of the present invention provides a trimming circuit based on the eighth aspect, wherein said first error correction circuit has a first input-per-output bit efficiency and said second error correction circuit has a second input-per-output bit efficiency which is higher than said first input-per-output bit efficiency.
According to the present invention, a tenth aspect of the present invention provides a trimming circuit based on the eighth aspect, wherein said first error correction circuit has a first error correcting capability, and said second error correction circuit has a second error correcting capability which is lower than said first error correcting capability.
According to the present invention, an eleventh aspect of the present invention provides a trimming circuit based on the eight aspect, wherein said first error correcting circuit comprises a majority decision circuit for making majority decision from said first data from a portion of said memory blocks.
According to the present invention, a twelfth aspect of the present invention provides a trimming circuit based on the eighth aspect, wherein said data includes error correction data, and said second error correction circuit error-corrects said second data from said memory circuit with said error correction data from said memory circuit.
According to the present invention, a thirteenth aspect of the present invention provides a trimming circuit for a physical quantity sensor comprising:
a memory circuit including a plurality of memory blocks for storing data including first and second data, each of said memory blocks including a memory;
a first error correction circuit for error-correcting said first data from said memory circuit through a first error correcting method;
a second error correction circuit for error-correcting said second data from said memory circuit through a second error correcting method, said first error correcting method being different from said second error correcting method; and
a weighting circuit for weighting an output of said first error correction circuit with a first coefficient to output a first trimming value for said physical quantity sensor and an output of said second error correction circuit with a second coefficient to output a second trimming value for said physical quantity sensor, said first coefficient being higher than said second coefficient.